The present invention relates to a semiconductor memory cell and, more particularly, to a semiconductor memory cell of a dynamic random access memory (DRAM) device composed of a single transistor and a stacked capacitor.
In 1970, a 1 kbit DRAM using for each cell three transistors and a charge-storing capacitor, referred to as 3T cell hereinafter, was invented. Since then, the history of the DRAM as a semiconductor memory of large capacity and low cost has evolved. Before that time, a flip-flop type SRAM was used as a semiconductor memory. If a MOSFET is used for the memory cell of an SRAM, 6 transistors or 4 transistors with two resistors are necessary. In contrast, the 3T cell of a DRAM uses only three transistors, so that it is more suitable for a semiconductor memory of large capacity having a small surface area. For a 4 kbit memory, the 3T cell has been replaced by a single transistor memory cell, referred to as 1T cell in the following, which is composed of a single transistor and a single capacitor. Thereafter, the technical improvement in the circuit design, device design, fine manufacturing and fabrication process has made a fourfold increase in the memory capacity of a DRAM with a 1T cell possible over a three year period. The scalling rule proposed in 1974 has promoted the technical improvement.
In 1978, a soft error phenomenon due to misoperation occurring on the occasion of invasion of alpha particles into the semiconductor was discovered, with the result that the design method of 1T cell has been obliged to change. Until that time, it was considered that the improvement in the fine manufacturing process and the development of the circuit design technique of a sense amplifier could decrease the capacitor composed of a 1T cell, referred to as a cell compacitor hereinafter, to a value assuring a stable read operation. However, it has been disclosed that in order to protect against soft error the cell capacitor has some lower limit. In other words, the cell capacitor has the necessary minimum value for protecting against soft error, in addition to the necessary minimum value conventionally known as value for assuring the stable read-out. For a DRAM with a capacity larger than 64 kbit, the necessary minimum value for protecting against soft error becomes a more significant factor for determining the cell capacitor, than that for assuring the stable read-out. Thus, the scaling rule cannot be applied to the cell capacitor. Consequently, since the area of memory cell cannot be decreased below some certain limit, the increase in memory capacity of a DRAM causes the gradual increase in memory chip surface area.
In 1982, a trench capacitor technique was developed, whereby the electrode area of the cell capacitor was increased by fabricating the capacitor in a trench. Resorting to this technique, the transistor area of a 1T cell can be decreased even though the cell capacitor remains as it is. This technique introduced the concept of three-dimensional design of a cell capacitor.
In order to enlarge the capcity of a DRAM using this technique, the size of the aperture of the trench capacitor should be made small and the depth of the trench should be made deep, however, the limitations of the processing technique may not afford a structure of this kind.
Recently, the stacked cell capacitor has entered into the limelight to overcome the limitations of the above-mentioned trench capacitor technique.
The construction of a 1T cell DRAM comprising a stacked cell capacitor is the same as that of the conventional 1T cell with respect to the transistor, word line and bit line. The surface of a P-type silicon substrate or a P-well fabricated upon a silicon substrate is divided into a device isolator region and an active region by, for example, LOCOS oxide film. The word lines are disposed nearly perpendicular to the longitudinal direction of the active region, while the bit lines are disposed nearly parallel to the active region. A transistor is fabricated in the active region. The transistor is composed of a gate electrode formed of a part of the word line, and first and second electrodes of N-type diffusion regions formed in a self-aligned relation with the gate electrode. The bit line is connected to the first electrode through the first contact hole. In a 1T cell DRAM comprising a stacked cell capacitor, its lower electrode is connected to the second electrode of the transistor through the second contact hole.
In the original 1T cell DRAM comprising a stacked cell capacitor, the bit line is disposed on the uppermost layer and the cell capacitor is disposed on the intermediate layer between the bit and word lines. The depth of the cell capacitor is sufficiently deep compared with those of the wiring layers, such as the bit and word lines. Accordingly, the size of the aperture of the first contact hole is small and its depth is extremely deep. As a result, a structure of this kind encounters the same problems associated with the trench structure.
Recently, in order to solve the aforementioned problem, a new structure of a 1T cell DRAM comprising a stacked cell capacitor has been proposed. Examples of this structure are shown in the IEDM Technical Digiest, pp. 592-595 (1988) and the IEDM Technical Digest, pp. 595-599 (1988). In these structures, the cell capacitor is disposed on the uppermost layer, and the bit line is disposed on the intermediate layer between the cell capacitor and the word line. Moreover, in these structures, the bit and word lines are disposed so as to avoid the upper surface of the second electrode while at the same time surrounding it. Therefore, the shape of the insulator film covering the bit line, word lines and the second electrode in the vicinity of the second contact hole constitutes a deep hollow. The second contact hole is constructed in the bottom of this deep hollow. Since the bit line is constructed above the word line, the depth of the deep hollow largely depends on the position of the bit line.
In the above-mentioned new structure of a 1T cell DRAM comprising a stacked cell capacitor, the distance between the bit line and the second contact hole is important. Thus, since the distance between neighboring bit lines is required to be large, the cell size of the memory device is limited.
Also, the position of the cell capacitor is determined by the position of the second contact hole, so that the disposition of the cell capacitor is limited.
Furthermore, although the thickness of the insulator film on the aperture of the second contact hole does not cause any problem, the controllability of the photolithography including the etching process is not sufficient because of the large thickness of the insulator film in the vicinity of the aperture portion.